In modern electronic systems, a buffer circuit between the host and peripheral (or the master device and the slave device) is often referred to as an input and output (I/O) interface circuit. A conventional I/O output status detection circuit of the interface circuit includes a hysteresis comparison circuit and a logic circuit. The I/O output status detection circuit operates in response to an enable signal, and the enable signal comes from the logic circuit. The I/O output status detection circuit compares amplitude of an output signal of the I/O interface circuit with a threshold value of the hysteresis comparison circuit to determine whether or not the output status of the I/O interface circuit is abnormal.
However, the threshold voltage of the hysteresis comparison circuit in the conventional solution is affected by the circuit configuration so that the accuracy of the threshold voltage is not too high that will affect the detection accuracy of the I/O output status detection circuit. In addition, the I/O output status detection circuit operates in response to an external enable signal, which only detects the output status of the I/O interface circuit when the enable signal is valid. However, the abnormal status of the I/O data bus may occur at any time. The conventional I/O output status detection circuit may not be desirable for completely detecting the output status of the I/O interface circuit.
The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.